The present invention relates to a semiconductor device, and in particular to a semiconductor device having a PoP (Package on Package) structure in which packages each having a semiconductor element mounted thereon are stacked. The present invention also relates to a manufacture method of such semiconductor device.
In recent years, the package has been reduced in size in order to reduce the size of semiconductor devices following the increase of the operation speed and capacity of the semiconductor devices. Particularly, in case of a portable equipment, use has been made of an MCP (Multi Chip Package) having a plurality of semiconductor elements mounted in the package. However, the MCP has a disadvantage in terms of cost since if one or more semiconductor elements in the MCP are defective, the other non-defective semiconductor elements are also treated as defectives. Preliminary inspection of the semiconductor elements themselves is possible. However, the distance between output terminals thereof is very small. This causes problems such as difficulty to set up a test jig, and possible cracks if silicon is used alone. Therefore, the PoP (Package on Package) technique is expected as an effective measure for solving such problems. According to the PoP technique, semiconductor elements are packaged in package, and the packages which have been inspected are stacked together.
FIG. 1 and FIG. 2 are side views showing a typical PoP structure. According to the PoP technique, a plurality of packages each having a semiconductor element sealed with a resin are stacked and these packages are connected through solder balls. The PoP structure shown in FIGS. 1 and 2 has two packages stacked together. The lower package is composed of a lower circuit board 4 which has solder balls 6 on its rear face, and has a semiconductor element portion 3 having a semiconductor element sealed therein with a resin and a connection land on its front face. The upper package is composed of an upper circuit board 2 which has a connection land on its rear face, and has a semiconductor element portion 1 having a semiconductor element sealed with a resin on its front face. The upper and lower wiring boards 2 and 4 are connected at their connection lands through the solder balls 6. The semiconductor element portion 3 is mounted in a central part of the upper surface of the lower package. In this case, the height of the solder balls 6 must be greater than that of the semiconductor element portion 3 of the lower package in order to prevent the rear face of the wiring board 2 of the upper package from abutting against the semiconductor element portion 3.
On the other hand, the solder balls for connecting the upper and lower packages are required to be smaller in size and to be arranged with narrower pitch in order to cope with the increase of connection terminals due to the enhancement of performance. However, since the sphericity of the solder balls is determined by the physical properties of the solder itself, it is impossible to intentionally form the solder balls into a shape elongated in a height direction. Further, there is a limit to decrease the thickness of the semiconductor element portion 3 of the lower package. Therefore, the increase of the number of the connection terminals inevitably leads to increase of the size of solder balls and increase of the dimensions of the package profile. In order to avoid such problems, Japanese Laid-Open Patent Publication No. H08-172144 (Patent Publication 1) proposes to form the circuit board 4 of the lower package into a concave shape, as shown in FIG. 2, by providing a board 4-1 in the periphery of the circuit board 4 so that the circuit board 4 is surrounded with banks. This package enables reduction of the solder ball size and narrowing of the pitch. However, this is not an optimal solution in view of the workability of the wiring board and the cost.
Cellular phones are one of principal applications of the PoP technique. By the nature of the cellular phones, importance is particularly placed on the reliability of connections when they are subjected to stress due to drop impact or the like. In order to improve the reliability of the connections, use is made of a method of alleviating the stress applied by impact to soldered portions by injecting underfill into the spaces between mounting boards and packages after completing the packaging process. In the case of a conventional MCP, only one connecting portion is placed between a mounting board and an interlayer portion of the MCP. In the case of a PoP, in contrast, two connecting portions are placed between a mounting board and a lower package, and between the lower package and an upper package. The injection of the underfill is carried out by the use of a thin nozzle so as to fill the space between the packages and the mounting board. In the case of a PoP, however, there is a problem that uniform injection cannot be obtained in a position between the lower package and the upper package unless more underfill than necessity is applied. This may cause various adverse effects such as warpage of the circuit board or the underfill spreading over and wetting a large area around the PoP. The underfill may be injected by using a jet nozzle, but this requires introduction of an additional apparatus.
Further, it is desired for the PoP that semiconductor elements to be mounted on the lower and upper packages can be selected and combined without any restriction. Since pad positions differ among the semiconductor elements, the lower and upper packages must be redesigned and produced as separate products. This will induce a problem of complicating the management in the mass production site. In contradiction to the demand for size reduction, the number of output terminals of the semiconductor devices mounted in portable equipment has been increased following the improvement in functions thereof. Therefore, there is a demand for a PoP structure suitable for mass production and yet capable of connection with narrow pitch so as to realize both multiple pins and size reduction.
There are more patent publications relating to a PoP technique as described below. According to Japanese Laid-Open Patent Publication NO. 2003-273321 (Patent Publication 2) and Japanese Laid-Open Patent Publication NO. 2003-218273 (Patent Publication 3), a circuit board having a semiconductor chip mounted is stacked with an interlayer board having an opening for accommodating the semiconductor chip, by means of bumps. Japanese Laid-Open Patent Publication NO. 2001-015627 (Patent Publication 4) discloses a technique in which an opening is formed in a package substrate, and a semiconductor chip is mounted in this opening. According to Japanese Laid-Open Patent Publication NO. 11-008334 (Patent Publication 5), a substrate sealed with a resin is cut off into sections to provide a single BGA (Ball Grid Array) package.